Presentation Slides

 

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Verilog Operators :

It's a compilation of the Appendix C given in the prescribed text book.

 

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Introduction to Logic Design :

It talks about different primitives and module design supported by Verilog HDl. Chapter 4 covers combinational logic circuits and associated delays in the real time system

 

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Behavioral Model of Combinational and Sequential Logic :

Chapter 5 gives a brief description of different design models including      Behavioral, RTL, Dataflow and Algorithm. This chapter also explains different loop constructs and subprograms like task and function.

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Synthesis of Combinational and Sequential Logic :

Chapter 6 provides the brief description about the synthesis tool and synthesis of latches and flip-flops in the combinational and sequential logics respectively. It gives an overview of bi-directional bus, explicit state machine and implicit state machine. It also includes static and non-static loops with or without the embedded timing controls.

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Design and Synthesis of Datapath Controller  :

Higher level architectures and the sequential machines can be partitioned in datapath unit and control unit. Chapter 7 considers RISC machine and UART as an example to explain the synthesis and design of an architecture in terms of datapath controller.

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Booth's Algorithm :

This is a small presentation just explaining the objective of Booth's algorithm, rules to implement the algorithm and finally an example showing execution order of the two data values.

 

 


Graduate Student (Electrical Engineering Dept., Temple University)

ayadav@temple.edu