1. IC74AC138 (1 to 8 Decoder).

  2. IC74F148 (8 to 3 Priority Encoder).

  3. MM74C922 (16 Key Encoder).

  4. MM74HC688 (8 bit Magnitude Comparator) - Students need to implement two more conditions as part of their project.

     a.    When data_1 is greater than data_2.

     b.     When data_1 is less than data_2.

  5. IC74AC151 (Multiplexer) - For the project, students will consider two multiplexers providing output data to a NAND gate for the final output .

                            *** Data sheets for all these IC's are available on Fairchild Semiconductors ***

  1. Up/Down Counter - Design a 8-bit up/down counter, which will have ports for 8-bits input, 8-bits output. The other control signals are input enable, up/down counter signal, reset and a clock. All state changes whether the parallel loading or in counting are initiated at the positive edge or rising edge of the clock. For the reference you can look into the datasheet of IC74F269(8-Bit Bidirectional Binary Counter).

  2. Stack - Design a stack which would be able to perform two protocols depending on the control signals.
    a. First in First out.
    b. Last in First out.
    Apart from clock and reset, student can implement their own control signals.

  3. Manchester Line Coding - Design an architecture which can emulate the Manchester line coding for serial data input.

  4. RZ Coding - Design an architecture which can emulate RZ (return to zero) coding for serial data input (For the reference student can either check on internet or appropriate communication book).

  5. Module for Seven Segment Display - Design an architecture which has single line input and provides 8-bit parallel output for seven segment display. For the seven segment display, students can refer datasheet of CD4511BC.

  1. Stack - As an extension of project 2, students have to implement one more protocol to their existing stack architecture.
    a. Random read and delete.

  2. Universal Shift Register - Design a universal shift register which would be able to perform following shift operations:
    a. Left shift.
    b. Right shift.
    c. Rotate right.
    d. Rotate left.
    Number of bits required for shift operation should be provided as an input.

  3. Asynchronous FSM - Design an asynchronous FSM that will detect the direction of rotation of a circular shaft as provided in the figure. Two light beams from the source l1 and l2 are caused to incident on the end surface of the shaft. The half portion of the shaft is reflecting and the other half is non reflecting. Two photocells A and B are mounted on proper reflecting angle so that whenever a beam strikes a reflecting surface photocell will generate voltage signal.

  4. Money Dispensing Machine - Design an architecture for a money dispensing machine (ATM), which will take an input from the user and provide the exact amount in terms of 20$, 10$ and 5$ bills.

  5. Speedometer - Design architecture for a speedometer, which indicates the speed level and provide the average of the speed when the engine of the car is turned off. It is assumed that the car has three different speed level for drive and whenever a brake is applied either it moves to one level down or stops completely. (Students can also add one level for the reverse drive, if they want).

  6. RGB to YIQ Converter - Design an architecture for RGB to YIQ conversion where RGB (red, green, blue) each contains 8-bit data. The data is clocked in at the rate of 48 bits/second. Students an google for information.

  1. Universal Shift Register with 8-bit Parity Generator/Checker - Design a universal shift register, which can rotate m-bits data for N number of times in either direction. The architecture should also have 8-bit parity generator and checker.

  2. Diagnostic Register with Booth Algorithm - Design and implement a Diagnostic register, which also has Booth algorithm for the multiplication. To understand the functionality of diagnostic register, students can refer to IC 74ACT818.( Data sheet for this IC is also available on ).

  3. Traffic Light Controller - Design a Traffic Light Controller, including an “emergency response” signal input and a traffic volume sensor to lengthen/shorten the time cycles.

  4. RMS Calculator - Implementation of “RMS” voltage calculator with 10-bit data signal input, mean (integration time) variable from 1 to 10msec in 1msec steps, square root (integer calculation) and 12-bit output (signed).

  5. Moving Average Filter - Design architecture to implement a “Moving Average Filter”. The architecture should consist of 10-bit signed input, average from 10 to 20 sampling intervals in 1 sampling interval step, auto normalized 12-bits output (signed).

  6. HE/D&SED/C - Design an architecture for (7,4) Hamming Encoder/Decoder and Syndrome Error Detection/Correction.