Verilog Examples

 

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Serial Line to Excess-3 Code Converter :

It's a code for a design which has single line input and 8-bit parallel output. Once a 8-bit data has been fetched, hexadecimal value "3" will be added to the value before providing it to the output port. (slc_code)

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Full Adder :

In this program, a module has been created for half adder, which has been instantiated twice with OR gate to simulate a Full Adder circuit. (Fulladder_code)

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If & Case Structure :

A same code has been simulated twice to display the implementation of "IF" and "Case" statement. (struct_code)

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Key Encoder :

This code simulates the architecture of IC-MM74C922 (20 Key Encoder) from Fairchild semiconductor. (key_code)

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Two Multiplexer with NANDed output :

This is an example of instantiating a module twice in the main module to implement the desired architecture. (mux_code)

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Feedback Oscillator :

This example indicates the different output behavior of Blocking and Non-Blocking operators. (FB_code)

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Speedometer :

This is an implementation of a speedometer, which also provides average speed when car is stopped. Three speed levels low, medium and high are considered for the implementation. (speedometer) .

 

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Booth's Algorithm:

 It's an implementation to generate the product of two 8-bit registers. This behavioral description follows all the rules defined by Booth's Algorithm

 

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