Ajay Kumar Yadav                                                                                                                                              

ajayky@gmail.com

Phone: 951-963-5324

 

SUMMARY

  • Extensive experience in Digital Circuit designing, testing, debugging and verifying system level architecture.
  • More than four years experience with Hardware Description Language (Verilog) and Processor level Designing.
  • Temple graduate with MS in Electrical Engineering. Extensive knowledge of Advanced Microprocessor and Digital designing on programmable devices (CPLD, FPGA).
  • Proficient with Model-Sim, ISE 8.0, Quartus II, Silos 2003, Warp 6.2, Matlab and other similar engineering tools.

EXPERIENCE

Avago Technologies, San Jose: IC Design Manager (Jan. 2014 – Present)

  • Adding to my IC design engineer responsibilities, leading a digital team for both front end and back end design flow.

Avago Technologies, San Jose: Digital IC Design Engineer (Feb. 2007 – Jan. 2014)

  • Designed and successfully taped out Multiple Modules for parallel Gigabit applications. Designed architectures are intended to support Infini Band, 10Gbps Ethernet and 4x XAUI Standards. All the modules are either in production or qualified for different applications.
  • Lead  a Parallel Transceiver Design which included multiple source serial interface, optical verification algorithm, memory bank and memory management, interrupt controller and closed loop feedback system for laser. Multiple scan chains and BIST modules were designed and tested for wafer level verification.
  • Implemented an Adaptive Digital algorithm which can detect the discrepancies in the input signal and auto correct it using the feedback from the error proxy block. Design is used for equalizing impairments induced on higher Gbps impaired signals.
  • Successfully implemented and verified an IP to measure the data Eye Quality and mask margin for 16G and 25G data rate. 
  • Delivered an IP which is Intel light peak compliant with self boot-up structure using one time programmable device. Design consists of data parity check state machine, auto DC cancellation loop, power management block, adaptive closed loop feedback for the LED. Challenge was to produce unified solution using multiple vendor requirements for different applications.
  • All the design also included industry compliant BIST machine for wafer level verification of the remote register and SRAM blocks.
  • Designs are synthesized and PNR (Place and Route) for 0.18u BiCMOS and 90nm CMOS technology. Experienced in both leading a team of engineers and using tools on both front and back end. Cadence tools (RC, Encounter, ATPG, LEC & Virtuoso) are used for back end development.
  • Played a key role in interfacing with Analog team (for mixed signal interface), Marketing team (For product requirement), Module team (For firmware development and module characterization), Production team (IC debugging and developing production test program).

ESS Technology, Irvine: System Engineer (Oct.2004 - Present)

  • Designed and coordinated a project to emulate 2Mega-Pixel sensor. Project required understanding of sensor design technology, signals and pixel data specification and interface requirements with the ISP(back end processor). Architecture was designed in Verilog-HDL and simulated & verified using Model-SIM. Synthesized architecture has been implemented on Stratix-II device and tested on a live system
  • Compiling and Debugging ASIC architecture to implement on Altera FPGA devices using Quartus II. Worked closely with the ASIC group on the behavioral code of image processing pipeline architecture to understand and build a system for initial research and development.
  • Designed a hardware platform which has USB and frame grabber interface and used for sensor characterization purpose. Architecture provides flexibility to control multiple programmable clocks, potentiometer and different switching devices using I2C bus.
  • Designed a memory (hardware) interface to store up to 1GB data and operates at two different clock speeds. Interface allows high speed video data to be read by slow speed devices.
  • Redesigning an interface to connect a KEIL system to the FPGA architecture for algorithm and firmware development.
  • Associated with the project of designing modular based testing platforms, used for VGA (Video Graphics Array) and 1-megapixel sensor modules. Tasks included designing a system to interface multiple boards operating at different voltages and redesigning old interfaces to make it compatible with the new platform. Other debugging job included removing ringing, and testing signal continuity and drive strength.
  • Working as an interface between Hardware and Firmware groups. Tasks involve identifying hardware design issues and their solutions with respect to firmware architecture.

Temple University, College of Engineering: Adjunct Faculty (08/03 - 08/04)

  • Designed and conducted a course and lab for Digital Circuit Design (EE156). The course included insight and understanding of Digital components and their implementation in different architecture. Labs included timing analysis and behavioral modeling using Verilog-HDL.
  • Designed and conducted  courses for Advanced Microprocessor using Verilog HDL (EE335) for senior and Digital Circuit Designing(EE135) for Junior level students . The main objective of the course is to introduce the Verilog-HDL and develop some architectures or digital circuit depending on their understanding and application. (Information is available on http://www.ajayky.info/335/Main.html).

Temple University, System-on-Chip Lab: Research Engineer (June. 2002 – Aug. 2004)

  • Designed and Synthesized CORDIC Algorithm and 16-bit Data Flow Controller as research projects targeting to Virtex chips from XIlinx.
  • Single handedly designed, synthesized and tested the behavioral architecture using Digilent Platforms (“XCV1000BG560” with 50MHz Clock) and HP logic wave analyzers.
  • Other projects included implementation of MIPS Pipelining for Multi-cycle Data path and Stack with Communication Protocol.

Patents

  • Adaptive Equalizer: An equalizer that includes a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima (Patent number: 9065696).
  • Method and apparatus for quantifying characteristics of a received serial data stream (patent 8744029).

Thesis/Recitation

implemented a DSP Core on the WDC 65C816 microprocessor (Spring-Fall, 2002)

  • Complete architecture of WDC 65C816 microprocessor has been modified and integrated with a DSP Core in Verilog-HDL and simulated in the Simucad, Silos 2001 environment.
  •  Main features of the DSP core included 16x16 bits Multiplier, 32 bits Product Register, 24-bits Accumulator, 8-bits Control Status Register, 8 new Op-codes and a Shifter.
  • Convergent Rounding method is added to the architecture to remove bias and maintain precision.
  • Generated Test benches for FIR and IIR filter to test the performance and verify the MAC operations in the newly designed DSP core.
  • Regular routine related to add, shift and memory read/write are tested to analyze the performance of micro-processor architecture in normal mode.
  • Timing analysis is performed for the above specified test benches during the simulation.
  • Final design has been implemented and tested on Delta 39K (FPGA) boards using WARP 6.0.

PROJECTS

Projects at ESS Technology:

Emulator Design: Designed and coordinated a emulator project to modulate and enhance the sensor image. Architecture has been tested on Altera FPGA to evaluate the performance and throughput. Assigned objectives included.

  • Regeneration of new control signals along with the pixel data as per the new specification without any discrepancies or latency in the streaming data.
  • Performing bi-linear interpolation on pixel data before regenerating the new image.
  • Providing features to change the operating modes or data format during the run time.
  • Providing a hardware support to test the design on a live system.

ASIC Interface: Designing a Verilog interface for the complete ASIC architecture and generating a code targeting to the Stratix II device of Altera using Quartus II. This project required:

  • Understanding of the image pipeline and flow of data through different modules/blocks.
  • Understanding of the core processor and I2C bus controller architecture
  • Complete mapping of the I/Os as per the image pipeline data flow, microprocessor and I2C controller.
  • Replacing RAM and PLL architecture with mega-functions provided by the Altera.
  • Verifying and testing the timing and propagation delay on the critical data paths.
  • Implementing the code on PROC-1S/2S (FPGA) module and verifying the behavior of the generated architecture. 

SDRAM Interface: This interface is designed to store up to 1GB of high speed sensor data (Video output) on SDRAM devices for image analysis. Interface allows data to be ported on the system at slower speed through USB interface. Design task included:

·         High speed data bus between the FIFO controller and four of the SDRAM (256MB) devices.

·         Programming CPLD to generate control signals and perform data error detection.

·         Initializing FIFO controller and providing flexibility for different configuration depending on the requirement.

·         Voltage stabilization for the fast switching circuits.

·         Generating read/write control signals for FIFO controller using either I2C bus or external jumpers.

·         Debugging and testing of the final architecture for any discrepancies.

 

KEIL Interface: This interface was designed to provide KEIL debugger capabilities for ASIC and firmware functional development and verification. Main task included:

·         Designing a architecture including devices like UART, EPROM, SRAM, multi channel RS232 driver, CPLD and Dorado (in-house processor).

·         Programming CPLD to generate control signals to different connecting devices.

·         Implementation of 16-bit bi-directional data bus and unidirectional address bus within the CPLD.

·         Designing a stable voltage circuit for reliable operation during the fast switching.

·         Providing the flexibility to run the system in different testing mode along with different configuration (Frame Grabber, USB and stand alone).

·         Identifying high speed or critical signals and buses for the length matching during PCB layout designing.

·         Debugging and testing of the board after fabrication and assembly to test the signals drive strength or any undesirable ringing and glitches.

KEYWORDS

Digital Design, System Design, ASIC, Verilog HDL, FPGA, Xilinx, Quartus, Altera, Virtex, Stratix, Microprocessor, DSP, Verification & Testing, Timing Analysis.

 

TECHNICAL SKILLS

Languages known:

ALP, Verilog-HDL, C,  HTML, Matlab script, Hilbert Script.

Operating Systems:

Windows 9x/3.x, Windows NT, Linux 6.2.

Tools:

Cadence Backend Digital Design Tools, Xilinx ISE 8.0, Warp 6.0& ISR 2.2 (Cypress semiconductor), EDA-Tanner, Logicwave Analyzer (HP, Agilent), Silos III (Simucad), Model-SIM & PADS (Mentor Graphics), OrCAD, Quartus II 6.0 (Altera), Matlab, Oscilloscope..

Miscellaneous:    

MS Word, Excel, Power Point, (MS Office), Hilbert Engine, SPSS.

 

EDUCATION

Temple University, PA.

 Master of Science, Electrical Engineering.

Cumulative G.P.A: 3.77

 

Course-work:

Advanced Microprocessor, Computer Architecture, Modern VLSI design, Computer Networking.

 

 P.E.S College Of Engineering, India

 Bachelor of Engineering,

Major: Electrical Engineering

Open to Travel and or Relocation