Verilog Projects.....!

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Course:Advanced microprocessors


20 Key Encoder:

This project was stimulating IC74C923, which is 20 key encoder. In this code truth table is used to generate corresponding output.


Stack controller:

This project is a stack controller with three protocols:
1. First in First out.
2. Random access data.
3. Random access, delete and reorder.


Address Generator for :

It generates the addresses for all the addressing modes of Western Design Center IC .Since this project was restricted with address generation, hence it w as more studying the internal architecture rather than the implementation. To get the required output certain assumption has been made in the program.


Course: Computer Architecture



MIPS single cycle datapath:

This is the implementation of MIPS single cycle datapath in Verilog. To make it easier, i have divided the complete program in five different modules, listed below.In the main program i have implemented each individual component of the diagra m of Chapter3 of the book Computer Architecture: Hardware interface. It executes R, I and J type of instructions.
1. Main Module
2. Data Memory
3. Program memory1
4. Program memory2
5. Program memory3
6. Test Bench


Thesis:


Design & Implementation of a DSP Core on WDC65C816
Microprocessor

A 16-Bit Fixed Point DSP Core will be designed and Implemented on WDC65C816 16-Bit Microprocessor. Verilog-HDL code of the complete Architecture of WDC65C816 and new Core will be generated and tested on Simucad SILOS III enviorment. For the Benchmarking verilog code will be downloaded on Delta39K Board using Cypress Semiconductor Warp(Version 6.0)tool. The proposed architecture and complete deatil of the work has been shown in the presentation slides.
Proposal Presentation>



**All the projects were synthesized on Silos III**


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